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Introduction to Logic Synthesis

Summary:

We study the synthesis of a gate-level implementation from an RTL specification. Here is a detailed course descriptor

Lecture Material

  1. Introduction
  2. Boolean functions
  3. Sum-of-Product representations (fix F')
  4. Exact 2-level minimization: Quine-McCluskey
  5. Heuristic 2-level minimization: ESPRESSO
  6. BDDs
  7. Multi-valued logic
  8. Multi-level logic circuits
  9. Factored forms
  10. Algebraic division
  11. Boolean division
  12. Using don't cares to optimize multilevel logic
  13. Technology mapping
  14. Timing analysis
  15. Timing optimization
  16. Sequential synthesis
  17. CNF-SAT
  18. Equivalence checking

Homeworks

  1. Homework 0: Fill out the biodata form pdf
  2. Homework 1: Boolean functions Due Monday 2.5.2007, in-class. Solution sketch.
  3. Homework 2: 2-level minimization Due Monday 2.12.2007, in-class.
  4. Homework 3: BDDs Due Wednesday 2.28.2007, in-class.
  5. Homework 4: BDD package Due Friday 3.23.2007, 5:00pm in my office
  6. Homework 5: Multi-level minimization: algebraic methods pdf
  7. Homework 6: Multi-level minimization: Boolean methods, technolog mapping pdf Due Monday 4.23.2007, in class. [Updated 1pm, 4.17.2007 - added problem 3, clarified XOR is 2 inputs.]
  8. Homework 7: Timing optimization pdf Due Wednesday 5.2.2007

Midterms

Term projects

Resources