Proc. IEEE Int. Conf. on Communications, Computers, and Devices, vol. 1, pp. 59-62, Dec. 14-16, 2000, Kharagpur, India.

The EASE Branch Predictor

Serene Banerjee, Lizy K. John, and Brian L. Evans

Department of Electrical and Computer Engineering, Engineering Science Building, The University of Texas at Austin, Austin, TX 78712-1084 USA
serene@ece.utexas.edu - ljohn@ece.utexas.edu - bevans@ece.utexas.edu -

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Abstract

Wide issue processors with many pipeline stages require efficient branch prediction for high throughput. In this paper, we propose an Embedded, Architecturally Simple and Efficient (EASE) branch predictor, which performs well for programs having a small number (100) and a large number (16,000) of instructions. EASE uses a combination of a G-share predictor and a one-level predictor. In EASE, one-level predictor is active until the G-share predictor warms up. For an example program of 100 instructions, the one-level, two-level, G-share, and EASE predictors give misprediction percentages of 36%, 38%, 41%, and 36%, respectively. The corresponding figures for an example program with 16,000 instructions are 9.5%, 5.6%, 3.3% and 3.3%, respectively. For the gcc benchmark, the EASE predictor outperforms hybrid and cascaded predictors by giving a misprediction percentage of 7.89%. When compared to hybrid and cascaded predictors, the EASE predictor has fewer counters and no decision circuitry, which makes it more efficient to implement in VLSI.

Last Updated 01/22/01.