Proc. IEEE Int. Workshop
on Signal Processing Systems,
pp. 343-348, Oct. 13-15, 2004.
Data Wordlength Reduction for Low-Power Signal Processing Software
Brian L. Evans
Earl E. Swartzlander, Jr.
Dept. of Electrical
and Computer Enginereing,
The University of Texas at Austin,
Austin, TX 78712 USA
Reducing power consumption prolongs battery life and increases
integration. In digital CMOS designs, switching activity
is closely connected with the total power consumption.
Switching activity on programmable processors implementing
linear filters, fast Fourier transforms, and other
signal processing operations is dominated by the hardware
multiplier. In this paper, we employ wordlength reduction
of multiplicands to reduce switching activity in hardware
multipliers using truncation and signed right shift methods.
For 32 bit x 32 bit Wallace and Radix-4 modified Booth
multipliers, truncation by 16 bits achieves a 4:1 and 2:1 reduction,
respectively, in switching activity, whereas signed
right shift gives little or no reduction. The key contribution
of this paper is the reduction of power consumption
by altering multiplicands in software without any hardware
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