This dissertation was presented to the Faculty of the Graduate School of The University of Texas at Austin in partial fulfillment of the requirements for the degree of
Ph.D. in Electrical Engineering
Analog-to-Digital Converter Circuit and System Design to Improve with CMOS Scaling
Yousof Mortazavi, Ph.D.E.E.
The University of Texas at Austin, May 2015
Prof. Arjang Hassibi and
Prof. Brian L. Evans
Defense Slides in PowerPoint and PDF formats
There is a need to rethink the design of analog/mixed-signal circuits to be viable in state-of-the-art nanometer-scale CMOS processes due to the hostile environment they create for analog circuits. Reduced supply voltages and smaller capacitances are beneficial to circuit speed and digital circuit power efficiency; however, these changes along with smaller dimensions and close coupling of fast-switching digital circuits have made high-accuracy voltage-domain analog processing increasingly difficult. In this work, techniques to improve analog-to-digital converters (ADC) for nanometer-scale processes are explored.
First, I propose a mostly-digital time-based oversampling delta-sigma ADC architecture. This system uses time, rather than voltage, as the analog variable for its quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital "pulse." The merits of this architecture render it not only viable to scaling, but also enable improved circuit performance with ever-increasing time resolution of scaled CMOS processes. This is in contrast to traditional voltage-based analog circuit design, whose performance generally decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage reduction and short-channel effects.
In conjunction with Dr. Woo Young Jung while he was a Ph.D. student at The University of Texas at Austin, two prototype implementations of the proposed architecture were designed and fabricated in TSMC 180 nm CMOS and IBM 45 nm Silicon-On-Insulator (SOI) process. The prototype ADCs demonstrate that the architecture can achieve bandwidths of 5-20 MHz and 50 dB SNR with very small area. The first generation ADC core occupies an area of only 0.0275 mm2, while the second generation ADC core occupies 0.0192 mm2. The two prototypes can be categorized as some of the smallest-area modulators in the literature.
Second, I analyze the measured results of the prototype ADC chips, and determine the source for the harmonic distortion. I then demonstrate a digital calibration algorithm that sufficiently mitigates the distortion. This calibration approach falls in the general philosophy of digitally-assisted analog systems. In this philosophy, digital calibration and post-correction are favored to traditional analog solutions, in which there is a high cost to the analog solution either in complexity, power, or area.
For more information contact: Yousof Mortazavi <firstname.lastname@example.org>