Embedded System Design and Modeling

EE382N.23, Unique: 16893
Semester: Fall 2015


 [1]  K. Keutzer, S. Malik, R. A. Newton, J. Rabaey, A. Sangiovanni-Vincentelli, "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), December 2000.
 [2]  L. Cai, S. Verma, D. Gajski, "Comparison of SpecC and SystemC Languages for System Design," Technical Report CECS-TR-03-11, University of California, Irvine, May 2003.
 [3]  W. Chen, X. Han, C.-W. Chang, R. Dömer, "Advances in Parallel Discrete Event Simulation for Electronic System-Level Design," IEEE Design & Test, vol. 3, no. 1, pp. 45-54, March 2012.
 [4]  W. Mueller, R. Dömer, A. Gerstlauer, "The Formal Execution Semantics of SpecC," International Symposium on System Synthesis (ISSS), October 2002.
 [5]  G. Berry, "The Esterel v5 Language Primer," INRIA, France, June 2000.
 [6]  E. A. Lee, "The Problem with Threads," IEEE Computer, vol. 39, no. 5, pp. 33-42, May 2006.
 [7]  G. Kahn, "The Semantics of a Simple Language for Parallel Programming," IFIP Congress on Information Processing, August 1974.
 [8]  T. M. Parks, Bounded Scheduling of Process Networks, Ph.D. dissertation, EECS, UC Berkeley, December 1995.
 [9]  M. Geilen, T. Basten, "Requirements on the execution of Kahn process networks", European Symposium on Programming Languages and Systems (ESOP), 2003.
 [10]  E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.
 [11]  S. S. Bhattacharyya, P. K. Murthy, E. A. Lee, "Synthesis of Embedded Software from Synchronous Dataflow Specifications," Journal of VLSI signal processing systems for signal, image and video technology, vol. 21, no. 1, pp. 151-166, June 1999.
 [12]  W. Thies, M. Karczmarek, S. P. Amarasinghe, "StreamIt: A Language for Streaming Applications," International Conference on Compiler Construction (CC), March 2002.
 [13]  D. Harel, "Statecharts: A Visual Formalism for Complex Systems," Science of Computer Programming, vol. 8, no. 2, pp. 231-274, June 1987.
 [14]  F. Vahid, S. Narayan, D. Gajski, "SpecCharts: A VHDL Front-End for Embedded Systems," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 14, no. 6, pp. 694-706, June 1995.
 [15]  L. Cai, D. Gajski, "Transaction Level Modeling: An Overview," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2003.
 [16]  L. Thiele, E. Wandeler, "Performance Analysis of Distributed Embedded Systems," Embedded Systems Handbook, 2005.
 [17]  O. Bringmann, W. Ecker, A. Gerstlauer, A. Goyal, D. Mueller-Gritschneder, P. Sasidharan, S. Sing, "The Next Generation of Virtual Prototyping: Ulta-fast Yet Accurate Simulation of HW/SW Systems," Design, Automation and Test in Europe (DATE), March 2015.
 [18]  S. Chakravarty, Z. Zhao, A. Gerstlauer, "Automated, Retargetable Back-Annotation for Host-Compiled Performance and Power Modeling," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2013.
 [19]  A. Gerstlauer, H. Yu, D. Gajski, "RTOS Modeling for System-Level Design," Design, Automation and Test in Europe (DATE) Conference, March 2003.
 [20]  P. Razaghi, A. Gerstlauer, "Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation," ACM Transactions on Embedded Computer Systems (TECS), 2014.
 [21]  A. Gerstlauer, D. Shin, J. Peng, R. Doemer, D. Gajski, "Automatic, Layer-based Generation of System-On-Chip Bus Communication Models," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 26, no. 9, pp. 1676-1687, September 2007.
 [22]  G. Schirner, R. Dömer: "Quantitative Analysis of the Speed/Accuracy Trade-off in Transaction Level Modeling", ACM Transactions on Embedded Computing Systems (TECS), vol. 8, no. 1, pp. 4:1-4:29, December 2008.
 [23]  A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski, J. Teich, "Electronic System-Level Synthesis Methodologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 10, pp. 1517-1530, October 2009.
 [24]  R. Doemer, A. Gerstlauer, J. Peng, D. Shin, L. Cai, H. Yu, S. Abdi, D. Gajski, "System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design," EURASIP Journal on Embedded Systems (JES), 2008.
 [25]  J. Lin, A. Gerstlauer, B. L. Evans, "Communication-Aware Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems," Journal of Signal Processing Systems, vol. 69, no. 3, December 2012.
 [26]  H. Topcuoglu, S. Hariri, M.-Y. Wu, "Performance-Effective and Low-Complexity Task Scheduling for Heterogeneous Computing," IEEE Transactions on Parallel and Distributed Systems, vol. 13, no. 3, pp. 260-274, March 2002.
 [27]  M. Gries, "Methods for Evaluating and Covering the Design Space During Early Design Development," Integration VLSI Journal, vol. 38, no. 2, pp. 131-183, December 2004.
 [28]  A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura, D. Araki, Y. Nishihara, "Specify-Explore-Refine (SER): From Specification to Implementation," Design Automation Conference (DAC), July 2008.

Additional references and documents are available for download in the Files section of Canvas.




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