EE382N Verilog Manual
Y. N. Patt, D. N. Armstrong
Department of Electrical and Computer Engineering
The University of Texas at Austin
Spring, 2002

Table of Contents

1. Introduction

In this class, we will be using the VCS Tool suite from Synopsys. The primary tools we will use will be VCS (Verilog Compiler Simulator) and VirSim, an graphical user interface to VCS for debugging and viewing waveforms. These tools are currently available on the Suns in the ECE LRC 5th floor lab, and will soon be available on Debian Linux boxes that are reserved for students in ECE computer architecture classes.

The methodology of debugging your project design involves three steps:
1) compiling your verilog source code,
2) running the simulation, and
3) viewing the generated waveforms.
The VCS tools will allow you to combine these steps to debug your design interactively.

VCS works by compiling your Verilog source code into object files, or translating them into C source files. VCS invokes a C compiler (cc, gcc, or egcs) to create an executable file that will simulate your design. This simulator can be executed on the command line, and can create a waveform file. Alternately, the design can be simulated interactively using VirSim, and the waveforms can be viewed as you step through the simulation.

The rest of this document will give a brief overview of the tools and show you how to compile and simulate the d-latch example from the EE382N Verilog manual. You should do this tutorial on one of the LRC Suns.