The University of Texas at Austin
Department of Electrical and Computer Engineering

VCS Manual

Table Of Contents

  1. 1. Introduction
  2. 2. Before You Start
  3. 3. Compiling and Simulating in Post-Processing Mode
  4. 4. Compiling and Simulating in Interactive Mode

1. Introduction

In this class, we will be using the VCS Tool suite from Synopsys. The primary tools we will use will be VCS (Verilog Compiler Simulator) and DVE, a graphical user interface to VCS for debugging and viewing waveforms. These tools are currently available on the ECE linux servers. Therefore you should ssh to any of the ECE linux machines to use the VCS tool suite.

The methodology of debugging your project design involves three steps:

  1. compiling your verilog source code,
  2. running the simulation, and
  3. viewing the generated waveforms.

The VCS tools will allow you to combine these steps to debug your design interactively.

VCS works by compiling your Verilog source code into object files, or translating them into C source files. VCS invokes a C compiler (cc, gcc, or egcs) to create an executable file that will simulate your design. This simulator can be executed on the command line, and can create a waveform file. Alternately, the design can be simulated interactively using DVE, and the waveforms can be viewed as you step through the simulation.

The rest of this document will give a brief overview of the tools and show you how to compile and simulate the D latch example from the EE 382N Verilog manual. You should do this tutorial on one of the ECE machines.

This document is by no means comprehensive. If it doesn't tell you what you want to know, we suggest you look through the documentation provided by Synopsis. There is a VCS user guide available on the machines in the directory: /usr/local/packages/synopsys_2012/vcs-mx/doc/UserGuide/pdf/vmm_user_guide.pdf . This user guide includes another tutorial for the VCS tools. This tutorial will explain additional features of the debugging interface that you may find useful for this class.

For debuging, the VCS 2012 package has the DVE tool (replaced old Virsim). Please invoke DVE as follows:

Interactive Mode compile time: >vcs <other options> -R -gui

Interactive Mode run time: >simv <other options> -gui

Post Process Mode: >dve &

2. Before You Start

You will need to use the following command to set up the environment from now on:

module load synopsys/vcs

If the above command fails, use the resetenv script to update your environment files to the latest ECE defaults. Your previous environment files will be saved in the ~/olddotfiles directory so that you can append your old settings to the new environment files.

You may also use the following command:

module initadd synopsys/vcs

to have the VCS environment set up automatically every time you log in to a linux machine.

Now that you can run VCS, create a directory where you want to put the files for this tutorial, and copy the following files into that directory:

3. Compiling and Simulating in Post-Processing Mode

  1. Change to the directory that you created for this tutorial.

  2. Compile the verilog source code by typing the following at the source prompt:

    vcs -debug_all -f master

    The -f option means that the file specified (master in this case) contains a list of command line options for vcs. In this case, the command-line options are mostly just a list of library file names.

    The following command line would have the same effect:

    vcs /home/projects/courses/spring_12/ee382n-16905/lib/time -v /home/projects/courses/spring_12/ee382n-16905/lib/lib1 d_latch.v

    The -v option before the library file means that only modules in the file that are actually instantiated (nand2$ and inv1$ in this case) will be compiled. When you ran this command, the output should have included the following:

    Top Level Modules:
     TimeScale is 1 ns / 10 ps
     Starting vcs inline pass...
     2 modules and 0 UDP read.
     Both modules done.
     ../simv up to date

    You should now have an executable file called simv in your working directory.

  3. Execute simv on the command line with no arguments. You should see output from both vcs and the simulation, and it should produce a waveform file called d_latch.dump in your working directory.

  4. Now we are going to view the waveform. At the prompt, type:


    Prior vcs versions used vcs -RPP d_latch.v for post-processing mode.

  5. You should now see DVE GUI window on your screen.

  6. In this window, click on Open Database under the File menu option. (VCD (.dump file extension) and VCD+ (.vcd file extension) files are both waveform files, but VCD files are text files, and VCD+ files are condensed binary files.)

  7. Select and open the file d_latch.dump, and then click OK. In the hierarchy window, you should see all TOP-level module instantiations: in this case, just latch1, which is the name of our D latch. Click on the TOP button, and you should see all signals instantiated at the TOP level in the signal window: d, q, qb, and we.

  8. Click on Add to Waves - New Wave View under the Signal menu option.

  9. In the Hierarchy window, all signals are shown and their waveform is shown in the right window starting at time 0 of the simulation. Most of them will be red at the beginning of the simulation, meaning they have the logic value “x”.

  10. In the waveform window, you can change the display unit (located on the toolbar right below the Simulator menu options). Change the display unit to 1 ns. You can also use the zoom buttons on the toolbar to zoom in or out and see more or less of the waveforms.

  11. You should be able to verify the functionality of the D latch and determine the propagation delays from the write-enable to the outputs and the data input to the outputs by examining the waveforms. For the library parts nand2$ and inv1$, the propagation delays are the same for rising and falling outputs. Is this true of the D latch?

  12. Because we used the system command $dumpvars (0, TOP); in our verilog simulation, we should be able to view all signals at any hierarchical level of the design. Hence if you go back to the hierarchy window and click on the plus symbol next to the latch1 button, you can traverse down the hierarchy and select more signals to view. If you highlight the button called latch1, you should see all signals and ports for the latch.

  13. Before exiting the waveform viewer, you can save your settings in a configuration file under the File -> Save Configurations option.

4. Compiling and Simulating in Interactive Mode

Now we are going to simulate the design again.

  1. Exit if you have not already. Recompile your source code with the following command line:

    vcs -debug_all -f master -R -gui &

    The -debug_all option allows to run the interactive dve tool and use steps to debug your design. When you use this option, it will create a sub-directory called csrc. This directory will contain a Makefile and object files for each module that is compiled. When you compile incrementally, which we suggest you do for your project, only the modules that change between compilations will need to be recompiled.

    The Interactive window of VirSim should have popped up by now. In the History panel, it says $stop at time 0. Whenever you invoke vcs with the -RI option, the simulation will always be paused at time 0.

  2. Open the Hierarchy window by clicking on Hierarchy under the Window menu. Our design had two modules at the highest level: TOP and timeunit. We are interested in looking at the TOP module. In the menu bar of the Hierarchy window, you will see a little tiny picture of a hierarchy. You can click on this to select the TOP module.

  3. From the main menubar, open the Waveform window, and either load your configuration file (using Ctrl-L) or browse through the hierarchy to select signals to view as in post-procession mode.

  4. In the Simulator Control panel in the Interactive window, change the Step Time to 1.00 to run the simulation in intervals of 1 ns. By clicking OK, you can step through the simulation.

  5. You can also step through the simulation until a specified time or until a specified signal (TOP.d, for example) changes value. When you simulate interactively, the waveforms are only recorded for the signals that appear in the Waveform Window. Hence you should select any signals of interest before the simulation time that you want to view them. If at any time you want to restart the simulation, select Re-exec or Invoke Sim under the Sim option in the Interactive window.

  6. You can also view your source code in the following manner. Click on Source under the Window menu. Then in the Hierarchy window, select a module instance, say TOP, and drag it (using the middle mouse button) to the large black panel in the Source window. If you want to edit your code, VCS will invoke a text editor (Edit -> Edit Source).

This should be enough to get you started on Problem set page. Let us know if you run into problems.