The University of Texas at Austin
Department of Electrical and Computer Engineering


Administrative Handouts

Exam 1 Preparation

Class Slides


This section lists the papers referenced in class. Some links may require you to login using your UT EID if accessed off-campus.

  • Processor Micorarchitectures

  • Out-of-Order and Superscalar

  • Mattan Erez et al.Spills fills and kills. An Architecture for Reducing Register-Memory Traffic.. Technical report Concurrent VLSI Architecture (TR-23), Stanford University, July, 2000.
  • Simultaneous Multithreading

  • Future Trends

  • Superblocks and Hyperblocks

  • Trace Cache

  • Cache Management Techniques

  • Runahead Execution

  • Branch Prediction

  • Predication

  • Block-Structured ISA

  • Cache Coherence

  • Consistency Models

  • Books

  • Patents

  • x86 ISA