Conventional DSP Architecture
Harvard architecture
- Separate data memory/bus and program memory/bus
- Three reads and one or two writes per instruction cycle
Deterministic interrupt service routine latency
Multiply-accumulate in single instruction cycle
Special addressing modes supported in hardware
- Modulo addressing for circular buffers (e.g. FIR filters)
- Bit-reversed addressing (e.g. fast Fourier transforms)
Instructions to keep the pipeline (3-4 stages) full
- Zero-overhead looping (one pipeline flush to set up)
- Delayed branches