PPT Slide
Conventional DSP Architecture (con’t)
Modulo addressing
implementing circular buffers and delay lines
Bit reversed addressing
used to implement the radix-2 FFT
xN-K+1
xN-K+1
xN-1
xN
Data-shifting
Time
Buffer contents
Next sample
xN+1
xN+3
xN+2
n=N
n=N+1
n=N+2
Modulo addressing
Time
Buffer contents
Next sample
n=N
n=N+1
n=N+2
xN-2
xN-1
xN-K+1
xN-K+2
xN-K+4
xN+1
xN+2
xN+3
xN-K+3
xN-K+4
xN+1
xN+2
xN-K+2
xN-K+3
xN
xN+1
xN-2
xN-1
xN+1
xN-K+2
xN
xN-2
xN-1
xN+1
xN+2
xN
xN
xN
xN
xN-K+3
xN-K+3
xN-K+4
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