TMS320C6x Pipeline

• One instruction cycle every clock cycle

• Deep pipeline

  • 7-11 stages in C62x: fetch 4, decode 2, execute 1-5
  • 7-16 stages in C67x: fetch 4, decode 2, execute 1-10
  • If a branch is in the pipeline, interrupts are disabled
  • Avoid branches by using conditional execution

• No hardware protection against pipeline hazards

  • Compiler and assembler must prevent pipeline hazards

• Dispatches instructions in packets

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