Pipelining

Managing Pipelines

• compiler or programmer (TMS320C6x)

• pipeline interlocking in processor (TMS320C30)

• hardware instruction scheduling

Sequential (Motorola 56000)

Pipelined (Most conventional DSP processors)

Superscalar (Pentium, MIPS)

Superpipelined (TMS320C6x)

Fetch

Read

Execute

Decode

Fetch

Decode

Execute

Fetch

Read

Execute

Decode

Fetch

Read

Execute

Decode

Previous slide

Next slide

Back to first slide

View graphic version