IEEE Transactions on Circuits and Systems II, vol. 63, no. 11, pp. 1049-1053, Nov. 2016.

A Mostly-Digital PWM-Based Delta Sigma ADC with an Inherently Matched Multi-Bit Quantizer/DAC

Yousof Mortazavi, Wooyoung Jung, Brian L. Evans and Arjang Hassibi

Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712 USA - - -



A mostly-digital PWM-based delta-sigma ADC is proposed. This system takes advantage of the duration pulses, rather than voltage or current, as the analog operand used in its closed-loop operation. Therefore, circuits that process the pulses are digital in nature and improve with scaling. Furthermore, the architecture allows inherently matched multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. A second novelty of this architecture is the modualtor's adapative excess delay, that synchronizes the asynchronous loop with an external reference clock. This mitigates the problems associated with non-uniform sampling. A first order 3-bit prototype of this architecture is presented. The core occupies an area of 0.0275 mm2 in 0.18 um CMOS process.

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Last Updated 12/02/16.