This dissertation was presented to the Faculty of the Graduate School of The University of Texas at Austin in partial fulfillment of the requirements for the degree of

Ph.D. in Electrical Engineering

Communication involves the transmission of information from one point to another through a series of processes. The three basic elements in each communication system are the transmitter, channel, and receiver. The transmitter and receiver are separated in space. A channel is the physical medium that connects the transmitter and receiver and distorts the transmitted signals in different ways. Severe distortions occur when data transmits through wireline channels. One way to counteract channel distortion in the transmission band is to employ an equalizer in the receiver.

This dissertation focuses on the design of channel equalizers in wireline communication systems. In particular, I consider equalization with and without channel estimation. When equalization is considered as a classification problem, neural networks can be used as equalizers without estimating the channel impulse response. I design a new neural network equalizer by cascading multilayer perceptron and radial basis function networks. In discrete multitone systems, the channel impulse response needs to be known at the receiver. Channel equalizers, a.k.a. time-domain equalizers (TEQs), are used to shorten the effective channel impulse response to a desired length. Channel impulse responses are generally infinite in extent. The long tails of the response are due to the poles of digital subscriber lines. I develop new matrix pencil methods to estimate the pole locations. Then, setting zeros of a TEQ at the locations of estimated poles is one way that I design a TEQ, which is possible with or without the knowledge of input training sequence. I also design divide-and-conquer TEQs which have lower computational cost than the current methods and give comparable performance in terms of shortening signal-to-noise ratio. The divide-and-conquer TEQs can be implemented on fixed-point digital signal processors.