Handouts

Administrative Handouts

• Student Information Sheet – please fill out this form, attach a recent recognizable photograph, and turn it in Monday, February 3rd.
• Class Auditor Permit – follow the instructions on this form if you want to officially audit the class
• Exam 1 and Exam 1 Solution

Papers

This section lists the papers referenced in class. Some links may require you to login using your UT EID if accessed off-campus.

• W. Daniel Hillis. The connection machine. 1985.
• J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, D. Shippy Introduction to the Cell multiprocessor . 2005.
• Intel. The Intel® Pentium® M Processor: Microarchitecture and Performance. 2003.
• Intel. The Microarchitecture of the Pentium 4 Processor. 2001.
• Tomasulo, R. M., An efficient algorithm for exploiting multiple arithmetic units , IBM J. Res. Dev. 11, 1 (Jan. 1967), 25-33
• Russell, R. M, The CRAY-1 computer system , Commun. ACM 21, 1 (Jan. 1978), 63-72.

• Simultaneous Multithreading

  • Burton Smith. “Architecture and applications of the HEP multiprocessor computer system,” Proc. SPIE, vol. 298 Real-Time Signal Processing IV, 1981, pp. 241-248.
  • Mario Nemirovsky, Forrest Brewer, Roger C. Wood. DISC: Dynamic Instruction Stream Computer. MICRO'91, 1991.
  • Donalson, D.; Serrano, M.; Wood, R.; Nemirovsky, M. DISC: dynamic instruction stream computer-an evaluation of performance System Sciences, 1993, Proceeding of the Twenty-Sixth Hawaii International Conference on , vol.i, no., pp. 448- 456 vol.1, 5-8 Jan 1993.
  • Yamamoto, W.; Serrano, M.J.; Talcott, A.R.; Wood, R.C.; Nemirosky, M. Performance estimation of multistreamed, superscalar processors System Sciences, 1994. Vol. I: Architecture, Proceedings of the Twenty-Seventh Hawaii Internation Conference on , vol.1, no., pp.195-204, 4-7 Jan 1994.
  • D.M. Tullsen, S.J. Eggers, H.M. Levy. Simultaneous Multithreading: Maximizing On-Chip Parallelism. Proceedings of ISCA-22, June 1995.
  • Robert S. Chappell, et. al. Simultaneous subordinate microthreading (SSMT). ISCA 26, 1999.
• Maurice V. Wilkes. “The Best Way to Design an Automated Calculating Machine,” Manchester University Computer Inaugural Conf., 1951.

  This paper is reproduced in the following books available from the UT library:

  • Earl E. Swartzlander, Jr. Computer Design Development: Principal Papers, Rochelle Park, N.J. : Hayden Book Co., 1976
  • M.R. Williams and Martin Campbell-Kelly. The Early British Computer Conferences. Cambridge, Mass. : MIT Press, 1989.
• Stephen W. Melvin and Yale N. Patt A clarification of the dynamic/static interface. 1987.

• Branch Prediction

  • James E. Smith, A Study of Branch Prediction Strategies Proceedings of the 8th International Symposium on Computer Architecture, 1981.
  • J.K.F. Lee, Alan J. Smith. Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer Vol. 17, Iss. 1, 1984.
  • Tse-Yu Yeh and Yale Patt. Two-Level Adaptive Training Branch Prediction. MICRO 21, 1991.
  • Tse-Yu Yeh and Yale Patt. Alternative implementations of two-level adaptive branch prediction. ISCA 1992
  • Shien-Tai Pan, Kimming So, Joseph T. Rahmeh. Improving the accuracy of dynamic branch prediction using branch correlation. ASPLOS-V, 1992.
  • Scott McFarling. Combining Branch Predictors. WRL Technical Note TN-36, DEC, 1993.
  • Ravi Nair. Dynamic path-based branch correlation. MICRO 1995.
  • Eric Sprangle, et. al. The Agree Predictor: A Mechanism For Reducing Negative Branch History Interference. ISCA 24, 1997.
  • Daniel A. Jiménez and Calvin Lin. Dynamic Branch Prediction with Perceptrons.HPCA 7, 2001.
  • Andre Seznec. Analysis of the OGEHL predictor. ISCA 32, 2005.
  • Andre Seznec, Pierre Michaud. A case for (partially) tagged Geometric History Length Branch Prediction. Journal of Instruction Level Parallelism, Feb. 2006.

• Out-of-Order and Superscalar

  • Daniel Gajski, David Kuck, Duncan Lawrie, and Ahmed Sameh. CEDAR: a large scale multiprocessor . ACM SIGARCH Computer Architecture News, 1983.
  • Joseph A. Fisher. Very Long Instruction Word architectures and the ELI-512. ISCA 10, 1983.
  • James E. Smith, Decoupled Access/Execute Computer. 1984. (revised journal version)
  • Yale Patt, Wen-mei Hwu, and Michael Shebanow. HPS, a new microarchitecture: rationale and introduction. MICRO'85, 1985.
  • Yale Patt, Stephen W. Melvin, Wen-mei Hwu, and Michael Shebanow. Critical issues regarding HPS, a high performance microarchitecture. MICRO'85, 1985.

• Dynamic Instruction Scheduling

  • Subbarao Palacharla, Norman P. Jouppi, J. E. Smith, Complexity-Effective Superscalar Processors. ISCA 24, 1997.
  • Jared Stark, Mary D. Brown, and Yale N. Patt, On Pipelining Dynamic Instruction Scheduling Logic. MICRO'00, 2000.

• Trace Cache

  • Stephen W. Melvin and Yale N. Patt. Performance benefits of large execution atomic units in dynamically scheduled machines. ICS 3, 1989.
  • Alexander Peleg and Uri Weiser. Dynamic flow instruction cache memory organized around trace segments independent of virtual address line. U.S. Patent 5381533, 1994.
  • Daniel H. Friendly, Sanjay J. Patel, and Yale N. Patt. Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. MICRO'97, 1997.
  • Sanjay J. Patel, Marius Evers, and Yale N. Patt. Improving trace cache effectiveness with branch promotion and trace packing. ISCA 25, 1998.
  • Eric Rotenberg, Jim Smith, and Steve Bennett. Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. MICRO'96, 1996.
  • Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and Jim Smith. Trace processors. MICRO'97, 1997.
  • Bryan Black, Bohuslav Rychlik, and John Paul Shenn. The block-based trace cache. ISCA 26, 1999.
• Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, and Jared Stark. One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer, 1997.
• Yale N. Patt. Requirements, Bottlenecks, and Good Fortune: Agents of Microprocessor Evolution. Proceedings of the IEEE, Nov. 2001.
• Steely Jr. et. al. Subroutine return prediction mechanism. US Patent 5,179,673, Jan 1993.
• Monreal. et. al. Late Allocation and Early Release of Physical Registers. IEEE Transactions on Computers, 2004.
• Andy Glew MLP yes! ILP no!. Wild and Crazy Idea Session ASPLOS, 1998.

• Cache Management Techniques

  • Moinuddin K. Qureshi, David Thompson, and Yale N. Patt The V-Way Cache : Demand-Based Associativity via Global Replacement. ISCA, 2005.
  • Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt. A Case for MLP-Aware Cache Replacement. ISCA, 2006.
  • Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., and Joel Emer. Adaptive Insertion Policies for High Performance Caching. ISCA, 2007.

• Runahead Execution

  • James Dundas and Trevor Mudge. Improving data cache performance by pre-executing instructions under a cache miss. ICS 11, 1997.
  • Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors. HPCA 9, 2003.
  • Onur Mutlu, Hyesoon Kim, and Yale N. Patt. Techniques for Efficient Processing in Runahead Execution Engines. ISCA 32, 2005.
  • Onur Mutlu, Hyesoon Kim, and Yale N. Patt. Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO'05, 2005.

• Post-Decode Cache

  • David R. Ditzel, Hubert R. McLellan, and Alan D. Berenbaum. The hardware architecture of the CRISP microprocessor. ISCA 14, 1987.

• Block-Structured ISA

  • Stephen Melvin and Yale N. Patt. Exploiting Fine-grained Parallelism Through a Combination of Hardware and Software Techniques. ISCA 18, 1991.
  • Eric Sprangle and Yale N. Patt. Facilitating superscalar processing via a combined static/dynamic register renaming scheme. MICRO 27, 1994.
  • Eric Hao, et. al. Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. MICRO 29, 1996.
  • Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, et al. Scaling to the End of Silicon with EDGE Architectures. IEEE Computer, 37 (7), 2004.

• Superblocks and Hyperblocks

  • Pohua P. Chang, Scott A. Mahlke, et al. IMPACT: an architectural framework for multiple-instruction-issue processors. ISCA 18, 1991.
  • Scott Mahlke, et al. Effective compiler support for predicated execution using the hyperblock. MICRO 25, 1992.

• Predication

  • Allen et. al., Conversion of control dependence to data dependence Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages, 1983.
  • Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution MICRO, 2005.

You can see the papers referenced in class for Spring 2008 and Spring 2006 semesters.

Class Slides

• EE382N Intro
• A science of tradeoffs
• Evolution of the uniprocessor
• Mechanisms:Run-time and compile-time
• Approaches to Concurrency
• Implications of multi-core

Previous Mid-term Exams

• Spring 2006
• Spring 2008

Buzzwords for first mid-term

• Buzzwords

x86 ISA

Look for the following x86 manuals (with 64-bit extensions) at Intel's Software Developer's Manuals webpage:

• IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture
• IA-32 Intel Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
• IA-32 Intel Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z
• IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide
• IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide

Alternatively, you may download the older manuals (without 64-bit extensions):

• IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture
• IA-32 Intel Architecture Software Developer's Manual Volume 2: Instruction Set Reference
• IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide

Other

• Project advice from former students