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Research

In general, I am fascinated by the tremendous possibilities offered by technological advancements in the area of embedded systems and systems-on-chip (SoCs). Think about all the neat little gadgets we will be able to build in the very near future!

However, it is well known that we are facing a growing productivity problem of designing systems that make use of all the available silicon estate. I am therefore interested in trying to close this gap by developing new methodologies and EDA/CAD tools to increase productivity on the designer's side. Technological advances and market pressures for higher integration make traditional design methods infeasible. Consequently, my research interests are focused on novel concepts and techniques for automation of the system design process at high levels of abstraction.

In general, my research is concerned with the development of electronic system-level (ESL) design methodologies, methods, technologies and corresponding design automation tools for embedded systems and SoCs. Results of this work have been going into the development of the SoC Design Enviroment (SCE), which integrates the resulting tools under a common GUI in order to implement a user-driven, interactive design flow from specification down to implementation. Furthermore, under the leadership of the Japanese Aerospace Exploration Agency (JAXA), a commercial derivative of SCE, called the Specify-Explore-Refine (SER) Studio, has been successfully deployed for use in JAXA's suppliers of space-electronic components.

In the future, I want to continue working on the design and synthesis of embedded systems. This should lead to a complete electronic system-level synthesis solution with support for advanced applications and target architectures, including embedded hardware and software synthesis, communication synthesis for network-on-chip architectures and hardware/software co-estimation.

With ever increasing software content, a critical challenge is the programming of multi-core and multi-processor systems. Building on the work on system design and synthesis, there is a unique opportunity to evolve system design tools into an embedded software development environment with automatic compilation of a high-level, abstract system programming model into distributed software, middleware and firmware running on a target platform consisting of multiple processors, cores and hardware IPs.

In the long term, I am especially interested in exploring the application of modeling, refinement, synthesis and estimation techniques to new classes of technologies and applications at the frontiers of embedded computing. In that aspect, I am looking forward to collaborations with researchers in other areas of computer science and engineering or other disciplines like the life sciences, physical sciences or other engineering fields.

System-Level Modeling and Languages

The basis of any automated design process is a well-defined design flow with semantically sound and unambiguous abstraction levels and design models. We originally developed and defined a novel, comprehensive set of system models for automatic, stepwise system design, refinement and synthesis. Formalized model definitions support the design process for complete multi-processor systems-on-chip (MPSoC) from abstract specification down to implementation, cumulating in a new generation of system-level design and synthesis tools.

I am also part of the SpecC project, an effort to develop a standardized system-level design language and methodology organized by the SpecC Technology Open Consortium (STOC) with members from industry and academia. Both SpecC language and methodology have been cited as major reference and inspiration for the development of SystemC, the leading, industry-standard system-level design and modeling language.

With system communication becoming increasingly important, transaction-level models (TLMs) have been proposed as a vehicle for abstraction and acceleration of communication design and validation. As part of the work on modeling, we developed, defined and analyzed one of the first applications of TLMs at various levels of abstraction. By adapting the separation of concerns outlined in the ISO/OSI layered model to the specifics of system-on-chip (SoC) and network-on-chip (NoC) communication, the approach supports automated design of communication architectures beyond a single shared bus. Resulting TLM definitions have been successfully adopted for modeling and synthesis of complete multiprocessor platforms. In general, all models have been developed to support further synthesis down to an actual implementation. We are currently in the process of investigating targeted synthesis of both software and hardware from our models down to the RTL or instruction-set level using a combination of existing and novel approaches for high-level synthesis and code generation.

Automatic Model Generation and System Synthesis

Traditionally, system models are manually written, which is a tedious, error-prone and time-consuming process. In attempts to supersede the need for dealing with coding details, based on research on model semantics, tools have been developed for automatic generation of network, transaction-level or pin-accurate system models. Given an abstract specification of the system together with system design decisions, tools automatically create customized and optimized protocol stack implementations inside the drivers and interfaces of software and hardware processors, respectively.

Model generation tools have been integrated under a common graphical user interface in the System-On-Chip Design Environment (SCE). Results obtained with SCE show that productivity gains of up to 1000x are possible.

SCE is continually being upgraded with additional input features and implementation options to support advanced, state-of-the-art applications and target platforms. For example, we plan to add support for extended channel semantics in the input application and for buffered communication network implementations including re-transmission and flow control in the presence of unreliable, long-latency communication media.

I intend to support SCE with the long-term goal of realizing a fully automated system synthesis solution. In combination with automatic model generation, this will incite research for the addition of decision making algorithms for automatic and optimized allocation, partitioning, scheduling and selection of communication parameters.

Embedded Processors and Hardware-dependent Software

An important goal of my work is support of the complete system design process for both hardware and software. To that effect, we developed for the first time a high-level, abstract model of real-time operating systems for integration of embedded software into standard system design flows. Abstract OS models are shown to be fast and accurate, enabling rapid, early validation of embedded real-time software. In the near future, we plan to continue work on RTOS modeling by extending the approach to include OS-internal timing and to support models of centralized or distributed operating systems in a symmetric or asymmetric multi-processing context.

Combining the approaches for abstraction of communication and computation, a complete model of the application software execution environment emerges. Such an abstract modeling of processors includes accurate representations of processor hardware, bus interfaces, firmware, drivers and operating systems. Results showed that depending on the feature level, speedups of up to 3 orders of magnitude with up to 97% accuracy can be achieved when compared to a traditional ISS-based software simulation.

Basic processor models are currently being augmented to support embedded software development in heterogeneous multi-processor and homogeneous multi-core environments. Furthermore, we are investigating methods for synthesis of high-level embedded software descriptions into final binary executables for each processor, targeting an off-the-shelf or custom RTOS in the process.

System-Level Estimation and Profiling

An essential aspect of efficient design space exploration is the availability of reliable and relevant design quality metrics at early stages in the design flow. We developed an approach for obtaining such metrics through a novel combination of dynamic profiling and static analysis of design models. Our approach to profiling is versatile in that it can deliver results for a variety of metrics at varying levels of abstraction. Results show that the profiler enables exhaustive exploration of large design spaces in a short amount of time while preserving 100% relative accuracy.

Future directions of this approach include true estimation by combining profiling results with an accurate model of the target processor microarchitecture, retargetable system-level co-estimation across hardware and software at varying levels of abstraction, and use of statistical methods in estimation to increase confidence in and reliability of results.