TI TMS320C6x VLIW DSP Architecture

Program RAM

Data RAM

or Cache

Internal Buses

Control Regs

Regs (B0-B15)

Regs (A0-A15)

.D1

.M1

.L1

.S1

.D2

.M2

.L2

.S2

CPU

Addr

Data

External

Memory

-Sync

-Async

DMA

Serial Port

Host Port

Boot Load

Timers

Pwr Down

Simplified Architecture

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