Spring 2007

EE 382V – System on Chip

LAB #4

Assigned: Nov 13, 2007

Due date: Nov 26, 2007

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0. NOTICE

             - Please use the discussion board of Blackborad (https://courses.utexas.edu/webapps/portal/frameset.jsp) for Q&A.

             - All reports/codes MUST be submitted to the Assignment section of the Blackboard.

1. Overview

The Goals of this lab are to

1) Analyze the software and design the equivalent hardware

2) Evaluate the performance, power and area of the hardware accelerator

The Assignment of this lab includes the following.

1) Inferring hardware from software

2) Estimating the area and power of the viterbi decoder hardware accelerator

3) Measuring performance improvement due to the hardware

2. LAB

 1) Tutorials

     A) Inferring hardware from software

Study the code of the butterfly module . The add-compare-select operation in the code is expressed by the tree structure. The basic idea is to convert the code into tree structures and infer the hardware. You will be optimizing the tree structure, if necessary, as part of your project.

     B) Measuring the area and speed of the viterbi decoder

The area and speed of this butterfly implementation can be estimated based on basic block library as in this example. Note that this library is derived using 0.18um technology. If you need additional macros, request the TA for the data of those macros.

     C) Simulating operations in CoMET

Please refer to the example for clock synchronized operation of peripherals in VaST tool. Pay attention to the "Add" function in example_display.h, study the code, run the project and observe the output for a better understanding of how to implement delays (for operations that involve multiple cycles) using the environment.

     D) Estimating the performance

Print the #clock cycles before and after the decode operation. The difference gives the #clock cycles for the decode operation.

     E) Estimating the power consumption

You may use the VLSI2 power template for power estimation. Any reasonable assumption can be made using this for your own purpose. Note that this spreadsheet corresponds to 0.13um technology, so appropriate scaling should be used. Detail the scaling computations in your report.

 2) Viterbi decoder

A) The viterbi decoder module from Lab3 must be modified as follows.

a. Convert your viterbi decoder module into a tree structure using the blocks given in basic block library. In your report, include a description of what software structures (if else, case, ifelsif, for, ...) correspond to what hardware structures (mux,...).

b. For every operation (add, compare, tree etc.) performed in the viterbi decoder, estimate and implement the delay in # of clock cycles as in this example (similar to tutorial C). In your report, include a diagram and a description of the hardware architecture (single-cycle, pipelined etc.) of your viterbi decoder. Also detail the operations/structures (add, compare etc.) and their corresponding delays.

c. Run CoMET simulation and verify the functionality as in LAB3. The output of the modified code should match the golden output.

d. Estimate the area of your viterbi decoder hardware.

e. Estimate the power of your viterbi decoder hardware.

B) Measure the #clock cycles taken for the decode operation for software implementation and hardware implementation (tutorial D) and report the performance improvement. You can also send data to the display module to print out the clock cycle. You must print the #clock cycles before and after the decode operation as part of your code.

3. Submission

In your report, include a brief summary of what you did for the lab. Include the tree structures of the viterbi decoder along with the performance improvement due to the hardware implementation. Also report the area and power consumption of the hardware module. Include the path of your working directory. This is a group lab and so one submission per group is sufficient.

Relevant Web Pages

                  Hardware optimized Viterbi Decoding algorithm

Design and implementation of a Viterbi decoder using FPGAs

Locally connected VLSI architectures for the Viterbi algorithm

A low complexity soft-output Viterbi decoder architecture