Michael Orshansky


  • Publications
  • Research
  • Teaching
  • Students
  • Variability-aware training and self-tuning of highly quantized DNNs for analog PIM
    Z. Deng, M. Orshansky. DATE 2022.
  • Power-based Attacks on Spatial DNN Accelerators
    G. Li, M. Tiwari, and M. Orshansky. JETC 2022.
  • Horizontal side-channel vulnerabilities of post-quantum key exchange and encapsulation protocols
    F. Aydin, A. Aysu, M. Tiwari, A Gerstlauer, M Orshansky. ACM Transactions on Embedded Computing Systems 2021.
    Top Pick in Hardware and Embedded Security 2021
  • Lattice PUF: A strong physical unclonable function provably secure against machine learning attacks
    Y. Wang, X Xi, M Orshansky. HOST 2020.
  • Training with multi-layer embeddings for model reduction
    B. Ghaemmaghami, Z. Deng, B. Cho, L. Orshansky, A. Singh, M. Erez, M. Orshansky. arXiv 2020.
  • A strong subthreshold current array PUF resilient to machine learning attacks
    H. Zhuang, X. Xi, N. Sun, M. Orshansky. TCAS 2019.
  • Fresh Securing AES against localized EM attacks through spatial randomization of dataflow
    G Li, V Iyer, M Orshansky. HOST 2019.
  • Fresh Using power-anomalies to counter evasive micro-architectural attacks in embedded systems
    S. Wei, A. Aysu, M. Orshansky, A. Gerstlauer, M Tiwari. HOST 2019. Best Paper Award Nomination
  • Fresh Re-keying with Strong PUFs: A New Approach to Side-Channel Security
    X. Xi, A. Aysu and M. Orshansky. HOST 2018.
  • Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange Protocols
    A. Aysu, M. Tiwari, and M. Orshansky. HOST 2018. Best Paper Award Nomination
  • Binary Ring-LWE Hardware with Power Side-Channel Countermeasures
    A. Aysu, M. Orshansky, and M. Tiwari. Design Automation and Test in Europe (DATE) 2018.
  • Efficient Helper Data Reduction in SRAM PUFs via Lossy Compression
    Y. Wang and M. Orshansky. Design Automation and Test in Europe (DATE) 2018.
  • Efficient Simulation of EM Side-Channel Attack Resilience
    A. Kumar, C. Scarborough, A. Yilmaz and M. Orshansky. International Conference on Computer-Aided Design (ICCAD) 2017. Best Paper Award Nomination
  • Strong Subthreshold Current Array PUF with 265 Challenge-Response Pairs Resilient to Machine Learning Attacks in 130nm CMOS
    X. Xi, H. Zhang, N. Sun, and M. Orshansky. VLSI Circuits Symposium 2017.
  • A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell
    S. Jeloka, K. Yang, M. Orshansky, D. Sylvester, D. Blaauw. VLSI Circuits Symposium 2017.
  • A new maskless debiasing method for lightweight physical unclonable functions
    A. Aysu, W. Wang, P. Schaumont, and M. Orshansky. Hardware-Oriented Security and Trust (HOST) 2017.
  • Exploiting randomness in sketching for efficient hardware implementation of machine learning applications
    Y. Wang, C. Caramanis, and M. Orshansky. ICCAD 2016.
  • Monte Carlo Simulation Flow for SEU Analysis of Sequential Circuits
    M. Li, Y. Wang, and M. Orshansky. DAC 2016.
  • PolyGP: Improving GP-Based Analog Optimization through Accurate High-Order Monomials and Semidefinite Relaxation
    Y. Wang, M. Orshansky, and C. Caramanis. DATE 2016.
  • Multiple Attempt Write Strategy for Low Energy STT-RAM
    J. Park and M. Orshansky. GLSVLSI 2016.
  • Novel Power Grid Reduction Method based on L1 Regularization
    Y. Wang, M. Li, X. Yi, Z. Song, M. Orshansky, and C. Caramanis. DAC 2015.
  • Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture
    Park, T. Zheng, M. Erez, and M. Orshansky. IEEE Transactions on VLSI 2015.
  • Multi-Level Approximate Logic Synthesis under General Error Constraints
    J. Miao, A. Gerstlauer, and M. Orshansky. ICCAD 2015.
  • Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization
    Y. Wang, M. Orshansky, and C. Caramanis. DAC 2014.
  • Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning
    K. Singh, K. He, C. Caramanis, and M. Orshansky. IEEE Transactions on CAD 2014.
  • Methods for Joint Optimization of Mask and Design Targets for Improving Lithographic Process Window
    S. Banerjee, K. B. Agarwal, S. Nassif, and M. Orshansky. SPIE Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3) 2013.
  • Timing-Error Acceptance for Design of Energy Efficient DCT/IDCT-Based Systems
    K. He, Gerstlauer, and M. Orshansky IEEE Transactions on Circuits and Systems for Video Technology 2013.
  • Approximate Logic Synthesis under General Error Magnitude and Frequency Constraints
    J. Miao, A. Gerstlauer, and M. Orshansky. ICCAD 2013.
  • Variable-Energy Write STT-RAM Architecture with Bit-Wise Write-Completion Monitoring
    T. Zheng, J. Park, M. Orshansky, and M. Erez. ISLPED 2013.
  • Approximate Computing: an Emerging Paradigm for Energy-Efficient Design
    J. Han and M. Orshansky. European Test Symposium 2013.
  • Novel Strong PUF Based on Nonlinearity of MOSFET Subthreshold Operation
    M. Kalyanaraman and M. Orshansky. HOST 2013. Best Paper Award Nomination.
  • Low-Energy Digital Filter Design Based on Controlled Timing Error Acceptance
    K. He, A. Gerstlauer, and M. Orshansky. ISQED 2013.
  • Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics
    A. K. Singh, K. Ragab, M. Lok, C. Caramanis, and M. Orshansky. Transactions on CAD 2012.
  • Modeling and Synthesis of Quality-Energy Optimal Approximate Adder
    J. Miao, K. He, A. Gerstlauer, and M. Orshansky. ICCAD 2012.
  • Low-Energy Signal Processing using Circuit-Level Timing-Error Acceptance
    K. He, A. Gerstlauer, and M. Orshansky. ICICDT 2012.
  • Controlled Timing-Error Acceptance for Low Energy IDCT Design
    K. He, A. Gerstlauer, and M. Orshansky. DATE 2011.
  • NBTI-Aware DVFS: A New Approach to Saving Energy and Increasing Processor Lifetime
    M. Basoglu, M. Orshansky, and M. Erez. ISLPED 2010.
  • Google Scholar Page and Complete Publication List