Sample simulator runs to help you in debugging your simulator
(Each of the hex files were simulated cycle by cycle using the "run 1"
command and an "idump" was performed after each cycle. *.dump files
show the cycle by cycle output of idump. *.state files summarize the
contents of the pipeline latches. *.timeline shows a timeline of the
execution of the program in the pipeline):
Note that these test cases are not meant to be exhaustive. You should
write your own test cases to make sure that your simulator is working
for every instruction and program.
You can use the following xfig files to show the changes you made to the datapath & state diagram. You can
modify these files using the xfig drawing program installed on LRC UNIX/Linux machines.
Change the declaration for int REGS[] in lc3bsim.c to
int REGS[LC3b_REGS] = {0,1,2,3,4,5,0x1236,0xABCD};
Run the simulator for the each of the following test cases for as many cycles as specified in
states.tests (column 3); and then do an rdump & mdump 0x1234 0x1244
Note: For grading, we did not check the value of the BUS in any of the
test cases. We did not check the value of the MDR for tests 16, 17,
19, 20, 25, 26, 28, 29 in Part A.