Spring 2007

EE 382V – System on Chip

LAB #4

NOT YET ASSIGNED

DEADLINE: Same as the project due date

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0. NOTICE

             - Please use the discussion board of Blackborad (https://courses.utexas.edu/webapps/portal/frameset.jsp) for Q&A.

             - All reports/codes MUST be submitted to the Digital DropBox of Blackboard.

1. Overview

The Goal of this lab is to

1) Understand HW/SW design tradeoffs.

2) Evaluate performance of the HW accelerator with the mectrics from PRD.

The Assignment of this lab includes the following.

1) Creating a synthesizable SystemC module.

2) Measuring an area of viterbi decoder.

3) Estimating performance improvement due to viterbi decoder.

2. LAB

 1) Tutorials

             a) Synthesizable SystemC module

A. Download butterfly test program shows both behavioral SystemC model and synthesizable SystemC model.

  Please take a closer look at the source code and run the program for better understanding.

          You should be able to notice that a synthesizable SystemC model is highly modularized and structured as in Verilog design.

B. The area and speed of this butterfly implementation can be estimated based on basic block library as in this example.

   Note that you may use this source code for both this lab and project.

C.       You may use the VLSI2 power template for power estimation.
                             Any reasonable assumption can be made using this for your own purpose.

             b) CoMET provides a way of profiling the performance of a design.

If you did NOT get through CoMET tutorial of Lab1, please do it NOW!

             c) This slide contains example of how to measure speed and power.

             d) Don't pay too much attention on optimizing size and speed. Converting to synthesizable code is first priority.
                 You will do optimization while you are doing project.

e) Please refer to following example for clock synchronized operation of peripherals in VaST tool. Note the "Add" function in example_display.h, study the code, run the project and observe the output for a better understanding of how to implement delays (for operations that involve multiple cycles) using the environment.

 2) Viterbi decoder

             a) The viterbi decoder module from Lab3 must be modified as follows.

A. Convert your viterbi decoder module into a synthesizable SystemC module using block in basic block library.

-  If you need any special block which is not in basic block library, such block should be written in Verilog and synthesized.

- This is the Verilog synthesis example in Design Compiler.

B. Estimate the area of your viterbi decoder and the speed of every sub module. You may try to optimize slack by using the smallest block for non-critical path.

C. For every operation of viterbi decoder, estimates the delay in # of clock cycles as in this example.

D. Run CoMET simulation and verify functionality as in LAB3.

b) Measure the # of cycles taken with pure software of MSCMLC for the golden input of LAB2/LAB3.

c) Measure the # of cycles taken with MSCMLC and viterbi decoder for the golden input of LAB2/LAB3.

      If you send any data to DISPLAY MODULE, it will print out the clock cycle.

3. Submission

Relevant Web Pages

                  Hardware optimized Viterbi Decoding algorithm

Design and implementation of a Viterbi decoder using FPGAs

Locally connected VLSI architectures for the Viterbi algorithm

A low complexity soft-output Viterbi decoder architecture