Fall 2018

EE 460R: Intro to VLSI Design

EE 382M-7: VLSI-1

Time: T/TH  14:00 - 15:30

Classroom: ECJ 1.318

Lab: EER 0.810

 

 

 

 


Course Goals:

We will be learning the methodologies of implementing a digital system as a CMOS integrated circuit. The course will begin with a review of the basics of CMOS transistor operation and the manufacturing process for CMOS VLSI chips. We will then study in detail the problem of implementing logic gates in CMOS. Specifically, we will cover layout, design rules, and circuit families. Afterwards, we will examine techniques for analyzing and optimizing timing and power at the circuit level. We will study sequential elements (latches and flip-flops) and clocking. This will be followed by an overview of datapath design: detection logic, shifters, comparators, adders, and multipliers. We will also study memories, specifically the workhorse 6-T SRAM cell as well as peripheral decode logic. The course will conclude with a survey level treatment of various topics, including advanced circuit design techniques, synthesis, timing analysis, functional verification, design-for-test, and future trends.

Application of the concepts studied in class to larger designs will be done via the computer-aided design laboratory exercises which are based on common industry design practice. Commercial tools and an open-source standard cell library are used for the labs. Laboratory exercises will enable students to learn all aspects of digital design, including: layout of simple cells and the generation of larger blocks using these cells; designs at the schematic level, and the use of timing verification tools; the use of automatic place-and-route tools, and the concepts of post-layout timing closure; design at the register-transfer level using the Verilog hardware description language; and the use of synthesis tools to generate the design details with a standard cell library.

There will be two in-class exams. All exams are open book and open notes. Several previous exams will be posted before the exam dates. There will be a final exam for EE460R. The team project replaces the final exam for EE382M-7.


Course prerequisites: 

A working knowledge of digital logic design (EE316), fundamentals of electronic circuits (EE438) is required.

Textbook


Instructor

Mark McDermott
Office: EER 5.826

Phone: 471-3253
Office hours: TBD

Teaching Assistant

Refer to TA web page for TA/grader office hours.

EE382M-7 Labs are located here

EE460R Lab assignments are located here


Course outline and schedule:

DATE

DAY

LECT. #

TOPIC

READING

HOMEWORK

LAB

Aug 30

Thu

1

Introduction

1.1 - 1.3

 

Lab. 1 Assigned

Sep 4

Tue

2

CMOS Fabrication and Layout

3.1 - 3.5

Homework 1

 

Sep 6

Thu

3

Implementing Logic in CMOS

1.4 - 1.5

 

 

Sep 11

Tue

4

MOS Transistor Theory

2.1 - 2.3.1

 

 

Sep 13

Thu

5

Non-Ideal MOS Transistors

2.4

Homework 2

 

Sep 18

Tue

6

DC and Transient Response

2.5

 

 

Sep 20

Thu

7

Logical Effort

4.4 - 4.5

 

 

Sep 25

Tue

8

Combinational Circuit Design

9.1 - 9.2.1.7

Homework 3

 

Sep 27

Thu

9

Clocking

13.4

 

Lab. 1 Due

 Lab. 2 Assigned

Oct 2

Tue

10

Latches and Flip-Flops

10.1 - 10.4

 

 

Oct 4

Thu

10

Latches and Flip-Flops

10.1 - 10.4

Homework 4

 

Oct 9

Tue

11

Interconnects in CMOS Technology

6.1 - 6.4

 

 

Oct 11

Thu

 

Exam I

Sample Exam

 

 

Oct 16

Tue

12

Adders 11.1 - 11.2

Homework 5

 

Oct 18

Thu

13

Datapath Design 11.3 - 11.10

 

 

Oct 23

Tue

14

Design for Testability

15.1

Homework 6

 

Oct 25

Thu

15

Power

5.1- 5.3

 

 

Oct 30

Tue

16

CAMs, ROMs, PLAs

12.4 - 12.7

 

 

Nov 1

Thu

17

Memory Elements

12.2 - 12.3

Homework 7

Lab. 2 Due

Lab. 3 Assigned

Nov 6

Tue

17

Memory Elements

12.2 - 12.3

 

 

Nov 8

Thu

 

Exam II

Sample Exam

 

 

Nov 13

Tue

18

VLSI Building Blocks

 

 

 

Nov 15

Thu

19

Circuit Pitfalls, Tips and Tricks

7.3, 9.3

Homework 8

 

Nov 20

Tue

20

 Hardware Description Languages

Appendix A

   

Nov 22

Thu

 

Thanksgiving

     

Nov 27

Tue

21

Introduction to Synthesis & Timing Analysis

 

Homework 9

Lab. 3 Due

Nov 29

Thu

22

Introduction to Design Verification

 

 

 

Dec 4

Tue

23

Scaling & Economics

7.4, 14.5

   

Dec 6

Thu

24

Course Review

Previous Final Exams

 

 

Grading:

Grading: 460R   Grading 382M
Homework 18% Homework 18%
Lab 1 10% Lab1 10%
Lab 2 10% Lab2 10%
Lab 3 12% Lab2 12%
Exam 1 15% Exam 1 15%
Exam 2 15% Exam 2 15%
Final Exam 20% Project 20%
Penalty for late submission: 5% per working day (maximum 25%, no submissions after 5 working days)

 


Additional Resources

Link to support material for the book

Link to papers and other stuff from Dave Harris

Read about the latest trends in VLSI design and CAD at EE Times

Deepchip.com is a great resource for VLSI CAD (lots of industry news and gossips)

Microwind is a nice public domain tool for VLSI design.

VLSI related papers.

Getting started with Linux

List of Linux machines


Reference Books:

Chandrakasan, Bowhill, Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2000.

Bernstein, et al., High Speed CMOS Design Styles, Kluwer Academic

Harris, Skew Tolerant Circuit Design, Morgan Kaufmann Publishers

V. G. Oklobdzija, The Computer Engineering Handbook, CRC Press, Boca Raton, Florida, 2002.

Weste & Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective (second edition), Addison Wesley


Academic dishonesty:


Oral discussion of homework problems is encouraged. However, be sure to submit your own individual and independent solution. Labs and final projects can be done in teams. Collaboration on projects is encouraged. Copying of any part of a homework/lab solution or project report without explicit reference to its source is plagiarism and considered cheating.

 

Electronic Mail Notification Policy:

In this course e-mail will be used as a means of communication with students. You will be responsible for checking your e-mail regularly for class work and announcements. The complete text of the University electronic mail notification policy and instructions for updating your e-mail address are available at http://www.utexas.edu/its/policies/emailnotify.html


Use of Canvas and Class Web Site

This course uses the class web page and Canvas to distribute course materials, to communicate and collaborate online, to submit assignments and to post solutions and grades. You will be responsible for checking the class web page and the Canvas course site regularly for class work and announcements. As with all computer systems, there are occasional scheduled downtimes as well as unanticipated disruptions. Notification of disruptions will be posted on the Canvas login page. Scheduled downtimes are not an excuse for late work. However, if there is an unscheduled downtime for a significant period of time, I will make an adjustment if it occurs close to the due date.



Students with disabilities

The University of Texas at Austin provides upon request appropriate academic accommodations for qualified students with disabilities. For more information, contact the Services for Students with Disabilities (SSD) at 471-6259, http://ddce.utexas.edu/disability/.


Religious Holidays

Religious holy days sometimes conflict with class and examination schedules. If you miss an examination, work assignment, or other project due to the observance of a religious holy day you will be given an opportunity to complete the work missed within a reasonable time after the absence. It is the policy of The University of Texas at Austin that you must notify each of your instructors at least fourteen days prior to the classes scheduled on dates you will be absent to observe a religious holy day.


Classroom Evacuation and Emergency Preparedness


All occupants of university buildings are required to evacuate a building when a fire alarm and/ or an official announcement is made indicating a potentially dangerous situation within the building. Familiarize yourself with all exit doors of each classroom and building you may occupy. Remember that the nearest exit door may not be the one you used when entering the building. If you require assistance in evacuation, inform your instructor in writing during the first week of class. For evacuation in your classroom or building:

Follow the instructions of faculty and teaching staff.
Exit in an orderly fashion and assemble outside.
Do not re-enter a building unless given instructions by emergency personnel.

Emergency evacuation route information and emergency procedures can be found at:

 http://www.utexas.edu/emergency     &     http://www.utexas.edu/safety/preparedness/

 


 Copyright 2001 - 2018 Mark McDermott