EE382M VLSI I (Spring 2009)

Instructor: Prof. David Z. Pan

VLSI I

Email: dpan@ece.utexas.edu

Spring 2009

Office: ACES 5.434; Phone: 471-1436

Unique No. 16675

Office Hours: Tue/Thu 3:00-4:00pm, or by appointment.

Lecture: TTH 12:30- 2:00pm at RLM 5.112

 

    • 4/5: The web site and dates have been updated.  Please pay attention to the new deadline and so on.
    • 3/5: The web site and dates have been updated.  Lab  2 deadline is extended to March 10.
    • 2/9: The web site and dates have been updated.
    • 2/5: Lab1 due date is now Thursday (2/12) midnight, not Tuesday. You have two days extension!
    • 1/24: Lab1 is assigned and TA web page is updated (with all the office hours, etc.)

Course Outline and Schedule (tentative)

Date

TOPIC OF LECTURE/DISCUSSION

Reading

HOMEWORK

LAB. ASSIGNMENT

EXAMS

Jan. 20

1. Introduction, CMOS Transistors

1.1-1.3

Homework 0

Lab. 1 Assigned

 

Jan. 22

2. CMOS Fabrication and Layout

3.1-3.5

 

 

 

Jan. 27

3. CMOS Logic

1.4-1.5

Homework 1

 

 

Jan. 29

4. MOS Transistor Theory

2.1-2.3.1

 

 

 

Feb. 3

5. DC and Transient Gate Characteristics

2.3.2-2.6, 4.2

Homework 2

 

 

Feb. 5

6. Logical Effort

4.3

 

 

 

Feb. 10

7. Combinational Circuits

6.1-6.2.1

Homework 3

 

 

Feb. 12

8. Design of Adders

10.1-10.2

 

Lab. 1 Due/ Lab. 2 Assigned 

 

Feb. 17

9. Datapath

10.3-10.10

Homework 4

 

 

Feb. 19

10. Interconnects in CMOS Technology

4.5-4.6

 

 

 

Feb. 24

11. Sequential Elements

7.1-7.5

 

 

 

Feb. 26

Sequential Elements (continued)

    

Notes

Homework 5 

 

 

Mar. 3

12.  Design Styles

 

 

 

 

Mar. 5

13. Hardware Description Languages, Synthesis

Notes

 

 

 

Mar. 10

14. Memories

11.1-11.3

 

Lab. 2 Due 

 

Mar. 12

 

 

 

Lab. 3 Assigned

Exam I;

Sample

March 16-20 Spring Break

 

Mar. 24

Continue on memory, etc.

 

 

 

 

Mar. 26

15. Dynamic CMOS Logic

6.2.2-6.2.5, 6.4-6.6

Homework 6 

 Project Selection Due

 

Mar. 31

16. Deep Submicron Issues

2.4

 

 

 

Apr. 2

17. CAMs, ROMs, PLAs

11.4-11.7

Homework 7 

 

 

Apr. 7

18. Circuit Pitfalls

6.3, 4.8

 

 

 

Apr. 9

19. Introduction to Test

9, Notes

 

  

 

Apr. 14

20. Packaging and I/O

12.2-12.4

 

 

 

Apr. 16

21. project discussion & Circuit Optimization

 

 

 Lab. 3 Due 

 

Apr. 21

22. Circuit Optimization

Notes

 

 

 

Apr. 23

23. Design for Low Power;

6.5

Homework 8

 

 

Apr. 28

24. Skew-Tolerant Design; mini-review

7.5-7.6, 12.5

 

 

 

April 30

 

 

 

 

Exam II

Sample

May 5

25. Scaling & Economics

4.9, 8.5

 

 

 

May 7

Project presentation & Summary

 

 

 

 

 

Projects

Additional Resources